As processors continue to increase in performance and throughput, the exchange of data from the memory devices to the processor can create a bottleneck in electronics and computing devices. One way to increase throughput is to increase the frequency at which memory signal lines (such as the data bus (DQ) and command/address bus (C/A bus)) are run. However, as signaling gets faster, the risk of errors increases due to the difficulty of meeting minimum margin guidelines at the higher frequencies. A failure to meet minimum margin guidelines can result in a failure on the command interface that is not detectable or correctable, which can cause silent data corruption.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.